1. Field of the Invention
The present invention relates to semiconductor integrated circuits containing programmable multi-level memory cell arrays, and particularly those arrays incorporating passive element memory cells, and more particularly those having a three-dimensional memory array.
2. Description of the Related Art
Writing and reading memory cells with more than two levels stored in each cell leads to performance penalties because multiple write cycles and multiple read cycles are required. In 3D passive element arrays this is a particular problem because of the other performance limitations in these arrays.
Other multi-level memory cells have been described, particularly three-terminal devices having a charge storage layer such as a floating gate. In these devices the gate terminal of the memory cell is usually coupled to a word line, and the various memory states are read by application of different voltages on the word line. At each such word line voltage, a current flows on the bit line if the word line voltage is above the programmed threshold voltage, and is sensed.
Certain passive element memory cells exhibit re-writable characteristics. For example, in certain memory cells programming may be achieved by forwarding biasing the memory cell (e.g., with reference to the polarity of a diode therewithin) with a voltage of approximately 6-8V, while erase may be achieved by reverse biasing the memory cell with a voltage of approximately 10-14V.